1. Field of the Invention
The present invention relates to a etching solution, and more particularly, to an etching solution capable of effectively reducing Galvanic effect.
2. Description of the Prior Art
In the latter manufacturing process of printed circuit boards and integrated circuits, usually using the photolithoetching technology with specific etching solution (e.g., ferric chloride etching solution, copper chloride etching solution or alkaline etching solution) so as to produce metal layer of specific pattern (i.e., wires or solder pads) on the printed circuit boards and integrated circuits. However, it would occur the undercut by using these etching solutions.
Please refer to FIG. 1 and FIG. 2, which illustrate schematic diagrams of manufacturing process of producing specific pattern on the printed circuit board. As FIG. 1 shows, in general manufacturing process of cooper wires of the printed circuit boards, firstly forming a etch-resisting layer 12′ having a specific pattern on the cooper layer 11′ of the substrate 10′; next, removing the cooper layer 11′ not covered by the etch-resisting layer 12′ through the wet etching process; finally, after removing the etch-resisting layer 12′, the cooper layer 11′ having the specific pattern would be formed on of the substrate 10′. However, as FIG. 2 shows, since the command of new generation products to the line width of the printed circuit board, the cooper layer 11′ covered by the etch-resisting layer 12′ would occur lateral etching when produce the extremely thin cooper wires, which is called undercut.
Besides, since the popularity of smart phones, tablet computers and consumptive electronic products, the traditional printed circuit boards using cooper wire to transfer signals are no longer affordable to the application of these consumptive electronic products. Therefore, a printed circuit board composited by cooper and gold has been provided in order to deal with the aforesaid problems of consumptive electronic products. Please refer to FIG. 3, which illustrates a top view diagram of the printed circuit board of gold and copper combination. As FIG. 3 shows, a copper wire 11″ and a gold wire 12″ are manufactured by a substrate 10″, wherein the reduction potential of the gold wire 12″ is higher than the reduction potential of the copper wire 11″; hence, the cooper layer 11″ connected to the gold wire 12″ would be over etched when produce the copper wire 11″ and the gold wire 12″ through wet etching process.
Accordingly, the inventor of the present application has made great efforts to make inventive research thereon and eventually provided an etching solution capable of effectively reducing Galvanic effect.